1. Field of the Invention
The present invention relates to a system in package device.
2. Description of the Related Art
(1) Problem of First System-in-Package Device
In recent years, in order to combine high performance and low cost of systems, techniques such as SoC (system on chip) where a system is formed on one chip and SIP (system in package) where a system is formed in one package have been developed (for example, see Jpn. Pat. Appln. KOKAI Publication Nos. 7-176684 and 2002-270759).
In the case of SoC, function blocks are formed on one chip.
It is, however, difficult to form the function blocks according to a common process. For example, in high-speed systems having a logic circuit and an interface circuit, the logic circuit is formed by a thin film CMOS process, and the interface circuit is formed by a thick film CMOS process.
For this reason, it is necessary to optimize the process and repress an increase in cost, but this becomes more difficult as the process generations roll by.
On the contrary, in SIP, a problem of the cost in the SoC does not arise.
In the case of SIP, since chips are formed in one package, a logic circuit and an interface circuit can be formed on different chips.
When the performance of systems becomes highly sophisticated, however, the number of chip terminals increases. For this reason, it is difficult to connect chips by wire bonding.
A technique for connecting chips using a bump is, therefore, proposed.
According to this technique, two chips having different functions are stacked via a bump. For example, a memory chip is arranged on a logic chip and both of them are connected to each other via a bump.
In this case, the upper chip is smaller than the lower chip and is flip-chip bonded to the lower chip. For this reason, the front face of the upper chip (the face on which an element is formed; the same applies to the following) faces the front face of the lower chip, and thus a signal terminal of the upper chip is not directly connected to an external terminal of the package.
That is, the upper chip transmits and receives a signal (except for a power-supply voltage) only to/from an element or a circuit formed in the lower chip.
In order to structure high-performance systems, however, the signal terminal of the upper chip is occasionally preferably connected directly to the external terminal of the package without an element or a circuit in the lower chip.
(2) Problem of Second System-in-Package Device
In recent years, in order to combine the high performance and the low cost of the systems, SIP (system in package) where a system is formed in one package has been developed (for example, see Jpn. Pat. Appln. KOKAI Publication No. 2001-24150).
In the case of SIP, since chips are formed in one package, a wiring technique for connecting the chips is important.
SIP includes a parallel type SIP in which chips are arranged in parallel and these chips are connected by a bonding wire, and stacking type SIP in which chips are stacked and these chips are connected by a bump.
In the case of the parallel type SIP, when the number of chip terminals increases according to the heightening of the performance of the systems, the chips cannot be connected to each other in the package.
On the contrary, in the case of the stacking type SIP, a micro-bump having a diameter of 100 μm or less is used so that even if the number of chip terminals increases, the connection of the chips can be sufficiently secured.
In the stacking type SIP, however, it is difficult to add a heat spreader to the package due to its structure.